Timing edge placement is often a critical parameter for high performance semiconductor testers. Having the ability to place the rising and/or falling edge of a test signal within a few picoseconds of a desired point in time may mean the difference in passing or failing large numbers of semiconductor devices under test.
Conventional timing generators that produce high accuracy timing signals are often employed in CMOS integrated circuits. CMOS technology provides relatively good performance at very low cost. However, CMOS ICs are often susceptible to temperature and other conditions that affect the performance of the circuit. To counter this, many CMOS timing generators employ sophisticated compensation techniques to minimize changes in delay.
With reference to FIG. 1, a conventional CMOS timing generator 10 that provides for temperature compensation typically includes a plurality of delay elements D1-DN coupled together to form a delay line. Each of the delay element outputs serve as timing selection inputs to a timing signal selector (not shown). The same outputs are also used for a delay compensation scheme. A compensation multiplexer 12 is employed, that receives the delay outputs, and provides an output to a phase detector 14, where it is compared to a reference signal Vref to determine any phase difference. A compensation voltage is then generated in response to the magnitude of any phase difference, and fed to a charge pump or voltage-to-current converter 16. The current generated by the converter is provided as bias current to the delay elements to control the delay.
FIG. 2 illustrates the conventional delay cell D1 in further detail. The basic cell is implemented by a differential pair of n-channel MOS transistors Qin1, Qin2 with MOS loads L1 and L2. A current source Ibias provides bias current through the differential pair and the loads. The loads comprise p-channel diode-connected MOS transistors Qdc11, Qdc12 in parallel with respective current source loads Qcs11, Qcs12. Typically, p-channel MOS transistors are desired for the loads because of the smaller capacitances normally associated with p-type transistors. A smaller capacitance is desirable at the differential outputs OUT1, OUT2 of the cell. In this configuration, the gate terminal G of the p-channel diode-connected load transistor is tied to the drain terminal D, with the source terminal S tied to VDD. The bulk substrate connection B is also tied to VDD.
While this configuration works well for its intended applications, the delay is often susceptible to jitter components acting on the VDD bus. Even a relatively small change of 0.1 volts can cause a corresponding change in the bias current through the cell, correspondingly affecting the delay characteristics of the cell.
What is needed and currently unavailable is a delay cell for use in a timing generator that causes minimal changes in delay that are attributable to jitter. The delay cell of the present invention satisfies this need.